It is well known in the art that errors frequently occur in pieces of data information stored in a memory device due to repeated write-in and read-out operations and alpha-particles emanating from packaging materials. In order to guard the pieces of data information against the errors, the pieces are coded in such a manner that the errors can be detected and even corrected by special logic circuits. FIG. 1 shows a typical example of a semiconductor memory device with the special logic circuit, or an error detecting and correction circuit.
Referring to FIG. 1 of the drawings, the semiconductor memory device comprises an input buffer circuit 1 operative to latch a piece of data information consisting of eight data bits I1 to I8 supplied from the outside thereof, a check-bit producing circuit 2 operative to append four check bits P1 to P4 to the data information supplied from the input buffer circuit 1, a memory cell group 3 provided with twelve memory cells M1 to M12 where the data information with the check bits is stored and having an address which is specified by row and column address signals X and Y, a write-in circuit 4 operative to decide whether or not the data information with the check bits should be written into the memory cell group 3 and to carry out a write-in operation in response to a write-in decision, a read-out circuit 5 operative to read out the data information with the check bits P1 to P4 from the memory cell group 3, an error detecting circuit 6 operative to detect whether or not the data information fed from the read-out circuit 5 has an error among the data bits and to identify the data bit with the error, an error correction circuit 7 operative to retrieve the correct data bit, and an output buffer circuit 8 operative to deliver the data information without the error data bit to the outside of the memory device.
Let the data bits of the data information with the check bits supplied from the red-out circuit 5 be represented by reference symbols D1 to D8. Reference symbols R1 to R8 stand for the respective data bits of the data information corrected by the error correction circuit 7. On the other hand, reference symbols Q1 to Q8 represent respective data bits of an output signal identifying the error data bit. In this example, the data information with the check bits consists of the eight data bits and the four check bits so that the error detecting circuit 6 is capable of identifying only one error data bit in the data information based on the four check bits.
Turning to FIGS. 2, 3 and 4 of the drawings, there is shown the circuit arrangements of the check-bit producing circuit 2, the error detecting circuit 6 and the error correction circuit 7. The check-bit producing circuit 2 comprises four exclusive-OR gates 11, 12, 13 and 14 and each of the exclusive-OR gates 11 to 14 has five input nodes to which preselected data bits of the data information is supplied, respectively. Namely, the exclusive-OR gate 11 is supplied with the five data bits I1, I4, I5, I7 and I8 and produces the check bit P1. Similarly, the exclusive-OR gate 12 is supplied with the five data bits I1, I2, I5, I6 and I8 to produce the check bit P2 and the exclusive-OR gate 13 is supplied with the data bits I2, I3, I5, I6 and I7 to yield the check bit P3. For producing the check bit P4, the data bits I3, I4, I6, I7 and I8 are supplied to the input nodes of the exclusive-OR gate 14, respectively.
The error detecting circuit 6 comprises four exclusive-OR gates 15, 16, 17 and 18 and eight AND gates 19, 20, 21, 22, 23, 24, 25 and 26. The exclusive-OR gate 15 is supplied with the five data bits D1, D4, D5, D7 and D8 and the check bit P1 and produces an output signal A, and the exclusive-OR gate is supplied with the five data bits D1, D2, D5, D6 and D8 and the check bit P2 to produce an output signal B. Likewise, the exclusive-OR gate 17 produces an output signal C on the basis of the five data bits D2, D3, D5, D6 and D7 and the check bit P3, and the exclusive-OR gate 18 is supplied with the data bits D3, D4, D6, D7 and D8 and the check bit P4 to yield an output signal D. Each of the AND gates 19 to 26 has four input nodes one or two of which is accompanied by a bubble or bubbles (indicating that an inverted input is received by the device along those lines) and the four input nodes are coupled to the output nodes of the four exclusive-OR gates 15 to 18, respectively. Namely, the AND gate 19 has the first and second input nodes directly coupled to the respective output nodes of the exclusive-OR gates 15 and 16 but the third and fourth nodes are accompanied by the bubbles and coupled to the output nodes of the exclusive-OR gates 17 and 18 through the bubbles. In a similar manner, the AND gate 20 has the first and fourth input nodes accompanied by the bubbles and the AND gate 21 has the first and second input nodes with the respective bubbles. The AND gate 22 has the second and third input nodes accompanied by the respective bubbles but the AND gate 23 is accompanied by only one bubble coupled to the fourth input node. Likewise, each of the AND gates 24, 25 and 26 is accompanied by one bubble coupled to the first, second or third input node. Then, the data bits mixed with the check bit are supplied to the exclusive-OR gates 15 to 18 for detecting whether or not the data information has an error bit and the AND gates 19 to 26 identify the data bit with error based on the output signals A to D fed from the exclusive-OR gates 15 to 18.
The error correction circuit comprises eight exclusive-OR gates 27, 28, 29, 30, 31, 32, 33 and 34 and each of the exclusive-OR gates 27 to 34 has two input nodes one of which is supplied with each data bit of the data information fed from the read-out circuit 5 and the other of which is supplied with each data bit of the output signal fed from the error detecting circuit 6. With the data bit of logic "0" level from the AND gate 19, 20, 21, 2, 23, 24, 25 or 26, each of the exclusive-OR gates 27 to 34 produces the data bit R1, R2, R3, R4, R5, R6, R7 or R8 identical in logic level to the data bit I1, I2, I3, I4, I5, I6, I7 or I8, however each exclusive-OR gate of the error correction circuit 7 produces the data bit opposite in logic level to the data bit of the data information fed from the read-out circuit 5. As described above, the output signal of the error detecting circuit 6 identifies the error bit, so that the exclusive-OR gates of the error correction circuit 7 retrieve the correct data bits in the presence of the data bits Q1 to Q8 of the output signal, respectively.
Description will be made in detail for error detecting and error correcting operations on the assumption that the data bits I1 to I8 of the data information have respective logic levels "0", "1", "0", "1", "0", "1", "0" and "1" (which is hereinunder referred to as (01010101) and are supplied to the input buffer circuit 1. When the data bits I1 to I8 of the data information are supplied to the check-bit producing circuit 2, the exclusiveOR gates 11 to 14 produces the check bits P1 to P4 which are (0101) because an exclusive-OR gate produces logic "0" in the presence of an even number of logic "1" inputs but logic "1" in the presence of an odd number of logic "1" inputs. As a result of specifying the address of the memory cell group 3, the writein circuit 4 allows the data information with the check bits (0101) to be stored in the respective memory cells M1 to M12 and, for this reason, the memory cells M1 to M12 store the data bits and the check bits of (01010101;0101), respectively. After a while, the memory cell group 3 is specified by the row and column address signals X and Y for read-out operation and the data information with the check bits is read out from the memory cells M1 to M12 to the read-out circuit 5. If no error occurs in the data information, the data information with the check bits ar (01010101; 0101). Then, the exclusive-OR gates 11 to 14 produces the output signals A to D which are (0000) because of the previously described exclusive-OR function. When the output signals A to D are (0000), all of the AND gates 19 to 26 produce the respective data bits Q1 to Q8 of the output signal (00000000) because of the bubbles coupled to the respective AND gates 19 to 26. With the output signal consisting of the data bits of (00000000), all of the exclusive-OR gates 27 to 34 produce the data bits R1 to R8 which are identical in bit string to the data bits I1 to I8. The data information consisting of the data bits R1 to R8 is transferred to the output buffer circuit 8 which in turn delivers the data information without any error data bit to the outside of the memory device.
On the other hand, an error occurs in the data information with the check bits stored in the memory cell group 3 and, for this reason, the data information has a bit string of (00010101:0101). When the data information with the error bit M2 is read out from the memory cell group 3, the exclusive-OR gates 16 and 17 produce the respective output signals B and C of logic "1" due to the error bit of logic "0". Then, the error detection circuit 6 produces the output signal of (01000000) which identifies the error bit stored in the memory cell M2. With the data bit Q2 of logic "1", the exclusive-OR 28 of the error correction circuit 7 produces the data bit R2 of logic "1" even if the data bit M2 has been inverted into logic "0". As a result, the semiconductor memory device can supply the outside thereof with the data information without error bit.
However, a problem is encountered in the prior-art semiconductor memory device in diagnostic operation for the error detecting circuit and the error correction circuit. This is because of the fact that the check bits are automatically produced by the check-bit producing circuit and, for this reason, it is impossible to provide a piece of data information with an error bit from the memory cell group to the error detecting circuit. This results in that the semiconductor memory device is doubtful in reliability.